A pervasive trend in modem integrated circuit manufacture is to increase the number of bits stored per unit area on an integrated circuit memory core that contains memory devices (sometimes referred to as memory cells), such as flash electrically erasable programmable read only memory (EEPROM) devices. For instance, a conventional semiconductor/oxide-nitride-oxide on semiconductor (SONOS) type memory device is capable of storing two bits of data in “double-bit” format. That is, one bit can be stored using a memory cell on a first side of the memory device and a second bit can be stored using a memory cell on a second side of the memory device.
An exemplary non-volatile SONOS-type memory device includes a semiconductor substrate with a source and a drain (both typically having N-type conductivity) formed therein. A body is formed between the source and the drain. An oxide-nitride-oxide (ONO) stack is formed above the body. A gate electrode, which typically comprises an N or N+ polysilicon layer, is formed over the ONO stack. The ONO stack includes a first or bottom dielectric layer (often referred to as a bottom tunnel oxide), a charge storing nitride layer, and a second or top dielectric layer.
Programming of such a SONOS device can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to each of the gate, the source, and the drain of the SONOS memory device for a specified duration until the charge storing layer accumulates charge. Such a process, with respect to a NOR architecture SONOS device is disclosed in co-owned U.S. Pat. No. 6,215,702, which is incorporated herein by reference in its entirety.
A conventional SONOS-type memory device, (e.g., having n N-type gate electrode and bottom oxide having a thickness of about 70 Å-100 Å), can only be erased using the conventional technique of “hot hole injection” (sometimes referred to as band-to-band (BTB) hot hole injection). In hot hole injection, a gate voltage of approximately −4˜−8 volts is applied along with a drain voltage on the order of 4.5-6.0 volts, while the source is floated or grounded to erase one of the memory cells (typically the normal bit). Conversely, the complementary bit cell is erased by floating the drain and applying the appropriate voltage to the source and the gate. With such erase conditions, a BTB tunnel current is created under the gate. Holes are generated under these conditions and accelerate from the N-type drain region into the P-type body. The generated holes are accelerated in the electrical field created near the P-N drain/body junction. Some of the accelerated holes surmount the oxide to silicon interface between the substrate and the bottom oxide and are injected into the nitride layer to displace electrons (e.g., by recombination) and erase the cell. However, as these hot holes bombard the interface between the substrate and the bottom tunnel oxide, the interface as well as the bottom tunnel oxide are damaged causing undesirable interface states and degraded reliability over program/erase cycling.
Another erase mechanism is channel erase (also commonly referred to as a Fowler-Nordheim (FN) erase). Typically, in conventional SONOS-type devices, the top and bottom oxides have the same dielectric constant, resulting in the vertical fields during the erase being the same across both the top and bottom oxides. Therefore, during an FN channel erase, electrons are pushed out from the charge storing layer to the substrate. However, because of the required erase voltage, electrons also flow from the N+ gate through the top oxide into the charge storing layer at approximately the same tunneling rate. Therefore, while there is a net current from the control gate to the substrate, charge is not erased effectively from the charge storing layer.
An attempt has been made to use channel erase with a SONOS-type architecture memory device having a very thin bottom tunnel oxide layer, (i.e., 30 Å or less). While less bottom oxide damage may occur with this erase mechanism, SONOS devices having a very thin bottom tunnel oxide suffer from data retention issues due to this thin bottom oxide. Of course, one of the most important concerns with EEPROM cells is data retention capability. Data retention is defined as the length of time a particular cell can retain information stored in the form of charge on the charge storing layer. Devices with very thin bottom oxide layers are susceptible to “low voltage leakage current,” which arises when electrons within the charge storing layer traverse the bottom tunnel oxide when no voltage is applied to the device. This small amount of leakage current may ultimately lead to total discharge of the cell.
Accordingly, there is an ever increasing demand for a SONOS-type memory device, which can be erased effectively, while still maintaining data retention capability.